System for distributing power in CPCI computer architecture

ABSTRACT

A system for distributing power in a compact peripheral component interconnect (CPCI) computer architecture is provided. A CPCI computer architecture comprises a plurality of CPCI systems each having respective backplanes. The backplanes further having respective local power rails providing power for a corresponding one of the plurality of CPCI systems. The power distribution system provides power to the backplanes, and comprises a common power rail connected to each one of the local power rails of the backplanes. A plurality of power supplies is connected to the common power rail of the power distribution system. Power taken from any one of the plurality of power supplies is available to any one of the backplanes.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to Compact Peripheral ComponentInterconnect (“CPCI”) computer systems. More particularly, the presentinvention relates to providing reliable power redundancy in a CPCIcomputer architecture.

2. Description of Related Art

CPCI is a high performance industrial bus based on the standard PCIelectrical specification in rugged 3U or 6U Eurocard packaging. CPCI isintended for application in telecommunications, computer telephony,real-time machine control, industrial automation, real-time dataacquisition, instrumentation, military systems or any other applicationrequiring high speed computing, modular and robust packaging design, andlong term manufacturer support. Because of its extremely high speed andbandwidth, the CPCI bus is particularly well suited for many high-speeddata communication applications such as servers, routers, converters,and switches.

Compared to standard desktop PCI, CPCI supports twice as many PCI slots(8 versus 4) and offers a packaging scheme that is much better suitedfor use in industrial applications. Conventional CPCI cards are designedfor front loading and removal from a card cage. The cards are firmlyheld in position by their connector, card guides on both sides, and afaceplate that solidly screws into the card cage. Cards are mountedvertically allowing for natural or forced air convection for cooling.Also, the pin-and-socket connector of the CPCI card is significantlymore reliable and has better shock and vibration characteristics thanthe card edge connector of the standard PCI cards.

Conventional CPCI defines a backplane environment that is limited toeight slots. More specifically, the bus segment of the conventional CPCIsystem is limited to eight slots, which includes a system slot andperipheral slots. The system slot provides the clocking, arbitration,configuration, and interrupt processing for up to seven peripheralslots.

As is commonly practiced in the art, redundant power is often providedto conventional CPCI computer systems in order to provide stability inthe event of power failure. In particular, it has become common in theart to provide redundant power to CPCI backplanes in the form of asecondary power supply. Within these CPCI systems, the primary andsecondary power supplies both deliver power to a local power rail on theCPCI backplane. As a result, the CPCI backplane is always provided withpower from one power supply in the event of a power failure in theother.

In order to accommodate systems using multiple backplanes, additionalpower supplies are ordinarily included in the art. In particular, theaddition of a second backplane typically requires the addition of asecond set of two power supplies. Similar to the aforementionedsingle-backplane architecture, a dual-backplane architecture routsredundant power to the first backplane by delivering power to the localpower rail of the first backplane directly from the first set of twopower supplies. Redundant power is then also routed to the secondbackplane by delivering power to the local power rail of the secondbackplane directly from the second set of two power supplies. As aresult, both backplanes are provided with power stability whenever asingle power supply fails within this architecture.

A drawback of this architecture is that it cannot support the emergenceof more sophisticated backplanes requiring an increasing amount ofpower. In particular, the dual-backplane architecture described above islimited in that the power available to either backplane is cut in halfwhenever one of its respective power supplies fails. As a result,backplanes requiring additional power (i.e., more than a single powersupply) do not have sufficient power within this type of architecture.

Accordingly, it would be advantageous to implement an architecture inwhich additional power, taken from any power supply connected to theCPCI system, is available to any of its backplanes.

SUMMARY OF THE INVENTION

The present invention relates to a system and apparatus for distributingpower in a compact peripheral component interconnect (CPCI) computerarchitecture. More specifically, a CPCI computer architecture comprisesa plurality of CPCI systems each having respective backplanes. Thebackplanes further having respective local power rails providing powerfor a corresponding one of the plurality of CPCI systems. A powerdistribution system provides power to the backplanes, and comprises acommon power rail connected to each one of the local power rails of thebackplanes. A plurality of power supplies is connected to the commonpower rail of the power distribution system. Power taken from any one ofthe plurality of power supplies is available to any one of thebackplanes.

A more complete understanding of a system and apparatus for distributingpower in CPCI computer systems will be afforded to those skilled in theart, as well as a realization of additional advantages and objectsthereof, by a consideration of the following detailed description of thepreferred embodiment. Reference will be made to the appended sheets ofdrawings which will first be described briefly.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a perspective view of a conventional CPCI chassis system;

FIG. 2 shows the form factor that is defined for the CPCI daughter card;

FIG. 3 is a front view of a conventional 3U backplane having eight slotswith two connectors each;

FIG. 4(a) shows a front view of a conventional CPCI backplane in the 6Uform factor;

FIG. 4(b) shows a back view of a conventional CPCI backplane in the 6Uform factor;

FIG. 5 shows a side view of the conventional backplane of FIGS. 4(a) and4(b);

FIG. 6 is a schematic diagram showing a conventional method forproviding power to a single backplane;

FIG. 7 is a schematic diagram showing a conventional method forproviding power to multiple backplanes;

FIG. 8 is a schematic diagram of an exemplary architecture fordistributing power to CPCI systems having two backplanes according to anembodiment of the invention;

FIG. 9 is a schematic diagram of an exemplary architecture fordistributing power to a variable number of backplanes according to anembodiment of the invention;

FIG. 10 is a schematic diagram of a current sense line implementationaccording to an embodiment of the invention; and

FIG. 11 is a schematic diagram of an input power isolation mechanismaccording to an embodiment of the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

The present invention satisfies the need for a CPCI system havingmultiple backplanes in which power is more efficiently distributed. Moreparticularly, the present invention provides an architecture in whichadditional power, taken from any power supply connected to the CPCIsystem, is available to any backplane. In the detailed description thatfollows, like element numerals are used to describe like elements shownin one or more of the drawings.

Referring to FIG. 1, there is shown a perspective view of a conventionalCPCI chassis system. The chassis system 100 includes a CPCI circuitboard referred to in the conventional CPCI system as a passive backplane102 since the circuit board is located at the back of the chassis 100and add-on cards (front cards) can only be inserted from the front ofthe chassis 100. On the front side of the backplane 102 are slotsprovided with connectors 104. In the conventional chassis system 100that is shown, a 6U daughter card 108 is inserted into one of the slotsand mates with a corresponding one of the connectors 104. For properinsertion of the daughter cards 108 into the slots, card guides 110 areprovided. This conventional chassis system 100 provides front removabledaughter cards and unobstructed cooling across the entire set ofdaughter cards 108.

Referring to FIG. 2, there is shown the form factor defined for the CPCIdaughter card, which is based on the Eurocard industry standard. Asshown in FIG. 2, the daughter card 200 has a front plate interface 202and ejector/injector handles 204. The front plate interface 202 isconsistent with Eurocard packaging and is compliant with IEEE 1101.1 orIEEE 1101.10. The ejector/injector handles should also be compliant withIEEE 1101.1. One ejector/injector handle 204 is used for 3U daughtercards, and two ejector/injector handles 204 are used for 6U daughtercards. The connectors 104 a-104 e of the daughter card 200 are numberedstarting from the bottom connector 104 a, and both 3U and 6U daughtercard sizes are defined, as described below.

The dimensions of the 3U form factor are approximately 160.00 mm byapproximately 100.00 mm, and the dimensions of the 6U form factor areapproximately 160.00 mm by approximately 233.35 mm. The 3U form factorincludes two 2 mm connectors 104 a-104 b, which is the minimum number ofconnectors that are required to accommodate a full 64 bit CPCI bus.Specifically, the 104 a connectors are reserved to carry the signalsrequired to support the 32-bit PCI bus, hence no other signals may becarried in any of the pins of this connector. Optionally, the 104 aconnectors may have a reserved key area that can be provided with aconnector “key”, which is a pluggable plastic piece that comes indifferent shapes and sizes, so that the add-on card can only mate withan appropriately keyed slot. The 104 b connectors are defined tofacilitate 64-bit transfers or for rear panel I/O in the 3U form factor.The 104 c-104 e connectors are available for 6U systems as shown in FIG.1. The 6U form factor includes the two connectors 104 a-104 b of the 3Uform factor, and three additional 2 mm connectors 104 c-104 e. In otherwords, the 3U form factor includes connectors 104 a-104 b, and the 6Uform factor includes connectors 104 a-104 e. The three additionalconnectors 104 c-104 e of the 6U form factor can be used for secondarybuses (i.e., Signal Computing System Architecture (SCSA) or MultiVendorIntegration Protocol (MVIP) telephony buses), bridges to other buses(i.e., Virtual Machine Environment (VME) or Small Computer SystemInterface (SCSI)), or for user specific applications. Note that the CPCIspecification defines the locations for all the connectors 104 a-104 e,but only the signal-pin assignments for the CPCI bus portion 104 a and104 b are defined. The remaining connectors are the subjects ofadditional specification efforts, or can be user defined for specificapplications, as described above.

Referring to FIG. 3, there is shown a front view of a conventional 3Ubackplane having eight slots with two connectors each. A CPCI system iscomposed of one or more CPCI bus segments, where each bus segmentincludes up to eight CPCI card slots. Each CPCI bus segment consists ofone system slot 302, and up to seven peripheral slots 304 a-304 g. TheCPCI daughter card for the system slot 302 provides arbitration, clockdistribution, and reset functions for the CPCI peripheral cards on thebus segment. The peripheral slots 304 a-304 g may contain simple cards,intelligent slaves or PCI bus masters.

The connectors 308 a, 308 b have connector-pins 306 that project in adirection perpendicular to the backplane 300, and are designed to matewith the front side “active” daughter cards (“front cards”), and“pass-through” its relevant interconnect signals to mate with the rearside “passive” input/output (I/O) card(s) (“rear transition cards”). Inother words, in the conventional CPCI system, the connector-pins 306allow the interconnected signals to pass-through from the front cards tothe rear transition cards.

Referring to FIGS. 4(a) and 4(b), there are shown a front and back viewof a conventional CPCI backplane in the 6U form factor, respectively. InFIG. 4(a), four slots 402 a-402 d are provided on the front side 400 aof the backplane 400. In FIG. 4(b), four slots 406 a-404 d are providedon the back side 400 b of the backplane 400. Note that in both FIGS.4(a) and 4(b) only four slots are provided instead of eight slots as inFIG. 3. Further, it is important to note that each of the slots 402a-402 d on the front side 400 a has five connectors 402 a-404 e whileeach of the slots 406 a-404 d on the back side 400 b has only fourconnectors 408 b-408 e. This is because, as in the 3U form factor of theconventional CPCI system, the 404 a connectors are provided for 32 bitPCI and connector keying. Thus, they do not have I/O connectors to theirrear. Accordingly, the front cards that are inserted in the front sideslots 402 a-402 d only transmit signals to the rear transition cardsthat are inserted in the back side slots 406 a-404 d through front sideconnectors 404 b-404 e.

Referring to FIG. 5, there is shown a side view of the conventionalbackplane of FIGS. 4(a) and 4(b). As shown in FIG. 5, slot 402 d on thefront side 400 a and slot 406 d on the back side 400 b are arranged tobe substantially aligned so as to be back to back. Further, slot 402 con the front side 400 a and slot 406 c on the backside 400 b arearranged to be substantially aligned, and so on. Accordingly, the frontside connectors 404 b-404 e are arranged back-to-back with the back sideconnectors 408 b-408 e. Note that the front side connector 404 a doesnot have a corresponding back side connector. It is important to notethat the system slot 402 a is adapted to receive the CPU front card, andthe signals from the system slot 402 a are then transmitted tocorresponding connector-pins of the peripheral slots 402 b-402 d. Thus,the conventional CPCI system can have expanded I/O functionality byadding peripheral front cards in the peripheral slots 402 b-402 d.

As previously stated, redundant power is ordinarily provided toconventional backplanes 400 in order to safeguard the system againstpower failures. In particular, redundant power is ordinarily provided byconnecting two power supplies to backplane 400 as shown in FIG. 6. Asillustrated, plugs 440 and 450 respectively mate with jacks 420 and 430in order to provide power from power supplies 460 and 470 to the localpower rail 410 of backplane 400. In the event of a power failure in oneof the power supplies 460, 470, it should be appreciated that sufficientpower is still provided to local power rail 410 by whichever powersupply remains functional. As a result, backplane 400 is thus providedwith power stability whenever a single power supply, 460 or 470, failswithin this architecture.

In order to accommodate systems using multiple backplanes 400,additional power supplies are ordinarily included in the art. Inparticular, the addition of a second backplane 402 typically requiresthe addition of two power supplies 462 and 472, as shown in FIG. 7.Similar to the aforementioned single-backplane architecture, adual-backplane architecture routs redundant power to local power rail410 from power supplies 460 and 470. Within this architecture, however,redundant power is also routed to local power rail 412 from powersupplies 462 and 472 by respectively mating plugs 442 and 452 with jacks422 and 432 as illustrated. As a result, backplane 402 is thus alsoprovided with power stability whenever a single power supply, 462 or472, fails within this architecture.

As previously mentioned, this architecture has drawbacks in supportingthe emergence of more sophisticated backplanes requiring an increasingamount of power. In particular, the architecture described in FIG. 7 islimited in that the power available to either backplane, 400 or 402, iscut in half whenever one of its respective power supplies 460, 470, 462,or 472 fails. As a result, backplanes requiring additional power (i.e.,more than a single power supply) do not have sufficient power withinthis type of architecture.

The present invention addresses these drawbacks by providing anarchitecture in which additional power, taken from any power supplyconnected to the chassis 100, is it available to any of the backplanesof the CPCI system. Referring to FIG. 8, there is shown a schematic of aCPCI power-sharing scheme in which power is equally available to allbackplanes in a chassis according to an embodiment of the invention. Asillustrated, power supplies 460, 470, 462, and 472 deliver power tobackplanes 400 and 402 via a power distribution printed circuit (PC)board 500. In particular, plugs 440, 450, 442, and 452 each respectivelymate with power distribution jacks 540, 550, 542, and 552, in order tocreate a common power rail 510 on power distribution PC board 500. Thiscommon power rail 510 is then connected to power distribution plugs 520,530, 522, and 532 which respectively mate with jacks 420, 430, 422, and432. As a result, power is provided to backplanes 400, 402 by all fourpower supplies 460, 470, 462, and 472 via a common power rail 510instead of only a particular pair of power supplies (e.g., powersupplies 460 and 470 for backplane 400, and power supplies 462 and 472for backplane 402). Within such embodiment, it should be appreciatedthat backplanes 400 and 402 equally share power between three powersupplies whenever any single one of the four power supplies fails.

It should be further appreciated that power distribution PC board 500may similarly be used to distribute power to a variable number ofbackplanes. Referring to FIG. 9, an example of how to distribute powerto a variable number of backplanes is provided according to anembodiment of the invention. As illustrated, additional backplanes 404,406, and 408 as well as additional power supplies 475 may be includedwithin this particular CPCI computer system. It should, be noted thatadditional power distribution plugs 535 as well as additional powerdistribution jacks 555 may be included to power distribution PC board500 as needed. In a preferred embodiment, power distribution PC board500 may thus be customized in order to accommodate CPCI configurationsrequiring a variable number of backplanes as well as a variable numberof power supplies.

Furthermore, it should be noted that backplanes 400, 402, 404, 406 and408 are each illustrated as respectively having a single jack 420, 422,424, 426, and 428. It should be apparent to those skilled in the artthat the dual-jack architecture of conventional backplanes is notnecessary within the described embodiment. Moreover, since powerprovided by all available power supplies is equally shared by allbackplanes via common power rail 510, only one jack is needed perbackplane. It should be appreciated that conventional backplanes havingdual-jack architectures may still be used within the describedembodiment. Preferred configurations would have only a single jack fromeach dual-jack backplane mate with a single power distribution plug inorder to make more efficient use of all available power distributionplugs.

As is commonly practiced in the art, current sense circuits are used toadjust the voltage and current of a particular backplane duringoperation. In particular, the power a backplane requires may varyaccording to the particular application being run. Current sensecircuits are then used to monitor these fluctuations in demand andadjust power accordingly. In another embodiment of the invention,current sense lines are used to provide output power isolation to theCPCI system as well as to variably adjust backplane power as needed.

Referring to FIG. 10, a schematic drawing is provided of a current senseline implementation according to another embodiment of the invention. Asillustrated, current sense lines 401, 403, 405, and 407 respectivelyconnect backplanes 400, 402, 404, and 406 to current sense circuits 521,523, 525, and 527 on power distribution PC board 500. Current sensecircuits 521, 523, 525, and 527 are then also respectively connected toswitches 531, 533, 535, and 537.

Current sense circuits 521, 523, 525, and 527 are respectively used toisolate backplanes 400, 402, 404, or 406 if an excessive amount of poweris being demanded (e.g., equivalent to a short circuit). Morespecifically, current sense circuits 521, 523, 525, and 527 willrespectively disconnect backplanes 400, 402, 404, or 406 from commonpower rail 510 via switches 531, 533, 535, and 537 whenever excessivepower is being demanded. It should thus be noted that, during normaloperation, switches 531, 533, 535, and 537 respectively provide power tobackplanes 400, 402, 404, and 406 by respectively connecting powerdistribution jacks 520, 530, 522, and 532 to common power rail 510. Ifan excessive demand in power is sensed by any one of the current sensecircuits 521, 523, 525, 527, corresponding switches 531, 533, 535, 537will open and thus disconnect the appropriate power distribution jack520, 530, 522, 532 from common power rail 510. As a result, the CPCIsystem is provided with an architecture that isolates a failed backplanefrom the rest of the CPCI system.

It should be appreciated that, in cases where power supplies without aninternal isolation mechanism are used (e.g., non-current-share powersupplies and some current-share power supplies), a method for providinginput power isolation to the CPCI system is desirable. In particular, itis desirable to include an input power isolation mechanism to CPCIsystems in order to protect against the malfunctioning of a powersupply. Referring to FIG. 11, a schematic drawing is provided of aninput power isolation mechanism according to another embodiment of theinvention. As illustrated, power distribution PC board 500 is modifiedto accommodate power supplies lacking an internal isolation mechanismthrough the use of diodes 541, 551, 543, and 553. More specifically,diodes 541, 551, 543, and 553 respectively connect power distributionjacks 540, 550, 542, and 552 to common power rail 510. It should beapparent to those skilled in the art that, by respectively connectingthe anodes of each diode 541, 551, 543, and 553 to power distributionjacks 540, 550, 542, and 552 and connecting the cathodes of each diode541, 551, 543, and 553 to common power rail 510 as shown, each powersupply 460, 470, 462, and 472 is provided with a power isolationmechanism within this architecture. In particular, it should be apparentto those skilled in the art that, by respectively connecting diodes 541,551, 543, and 553 as described above, any malfunctioning power supplywill not be able to prevent the remainder of the CPCI system fromfunctioning. Furthermore, it should be appreciated that, although diodesare used within this particular embodiment, any of several types ofrectifying methods known in the art may be implemented as well.

Having thus described a preferred embodiment of a system and apparatusfor distributing power in CPCI computer systems, it should be apparentto those skilled in the art that certain advantages of the within systemhave been achieved. It should also be appreciated that variousmodifications, adaptations, and alternative embodiments thereof may bemade within the scope and spirit of the present invention. The inventionis further defined by the following claims.

What is claimed is:
 1. A compact peripheral component interconnect(CPCI) computer architecture, comprising: a plurality of CPCI systemseach having respective backplanes, said backplanes further havingrespective local power rails providing power for a corresponding one ofsaid plurality of CPCI systems; a power distribution system providingpower to said backplanes, said power distribution system comprising acommon power rail connected to each one of said local power rails ofsaid backplanes; and a plurality of power supplies connected to saidcommon power rail of said power distribution system; wherein power takenfrom any one of said plurality of power supplies is available to any oneof said backplanes.
 2. The CPCI computer architecture of claim 1,wherein said local power rails of said backplanes each further comprisea plurality of power jacks.
 3. The CPCI computer architecture of claim2, wherein said common power rail further comprises a plurality ofdistribution plugs adapted to be connected to said plurality of powerjacks of said backplanes.
 4. The CPCI computer architecture of claim 1,wherein said common power rail further comprises a plurality ofdistribution jacks adapted to be connected to said plurality of powersupplies.
 5. The CPCI computer architecture of claim 1, wherein saidpower distribution system further comprises a printed circuit (PC)board.
 6. The CPCI computer architecture of claim 1, wherein said powerdistribution system further comprises a plurality of current sensecircuits connected to respective ones of said backplanes.
 7. A compactperipheral component interconnect (CPCI) computer architecture,comprising: a plurality of CPCI systems each having respectivebackplanes, said backplanes further having respective local power railsproviding power for a corresponding one of said plurality of CPCIsystems; a power distribution system providing power to said backplanes,said power distribution system comprising a common power rail connectedto each one of said local power rails of said backplanes; and aplurality of power supplies connected to said common power rail of saidpower distribution system: wherein power taken from any one of saidplurality of power supplies is available to any one of said backplanes;wherein said power distribution system further comprises a plurality ofcurrent sense circuits connected to respective ones of said backplanes;and wherein said power distribution system further comprises a pluralityof switches coupled with said current sense circuits at least one ofsaid current sense circuits controlling at least one of said switchesand each of said plurality of switches being adapted to disconnect powerfrom said power distribution system to a corresponding one of saidbackplanes upon detection of an excessive amount of power demanded bysaid corresponding one of said backplanes.
 8. The CPCI computerarchitecture of claim 3, wherein said distribution plugs are connectedto said common power rail via respective input power isolation circuits.9. The CPCI computer architecture of claim 8, wherein said input powerisolation circuits further comprise respective diodes.
 10. The CPCIcomputer architecture of claim 1, wherein ones of said backplanesfurther comprise a plurality of slots, each of said slots comprising ofat least one connector and each of said connectors having a column androw arrangement of connector-pins.
 11. A power distribution system foruse in a compact peripheral component interconnect (CPCI) computerarchitecture comprising a plurality of CPCI systems each havingrespective backplanes, said backplanes further having respective localpower rails providing power for a corresponding one of said plurality ofCPCI systems, said power distribution system comprises: a powerdistribution board providing power to said backplanes, said powerdistribution system comprising a common power rail connected to each oneof said local power rails of said backplanes; and a plurality of powersupplies connected to said common power rail of said power distributionsystem, wherein power taken from any one of said plurality of powersupplies is available to any one of said backplanes.
 12. The powerdistribution system of claim 11, wherein said local power rails of saidbackplanes each further comprise a plurality of power jacks.
 13. Thepower distribution system of claim 12, wherein said common power railfurther comprises a plurality of distribution plugs adapted to beconnected to said plurality of power jacks of said backplanes.
 14. Thepower distribution system of claim 11, wherein said common power railfurther comprises a plurality of distribution jacks adapted to beconnected to said plurality of power supplies.
 15. The powerdistribution system of claim 11, wherein said power distribution boardfurther comprises a printed circuit (PC) board.
 16. The powerdistribution system of claim 11, wherein said power distribution boardfurther comprises a plurality of current sense circuits connected torespective ones of said backplanes.
 17. A power distribution system foruse in a compact peripheral component interconnect (CPCI) computerarchitecture comprising a plurality of CPCI systems each havingrespective backplanes, said backplanes further having respective localpower rails providing power for a corresponding one of said plurality ofCPCI systems, said power distribution system comprises: a powerdistribution board providing power to said backplanes, said powerdistribution system comprising a common power rail connected to each oneof said local power rails of said backplanes; and a plurality of powersupplies connected to said common power rail of said power distributionsystem; wherein power taken from any one of said plurality of powersupplies is available to any one of said backplanes; wherein said powerdistribution board further comprises a plurality of current sensecircuits connected to respective ones of said backplanes; and whereinsaid power distribution board further comprises a plurality of switchescoupled with said current sense circuits, at least one of said currentsense circuits controlling at least one of said switches and each ofsaid plurality of switches being adapted to disconnect power from saidpower distribution board to a corresponding one of said backplanes upondetection of an excessive amount of power demanded by said correspondingone of said backplanes.
 18. The power distribution system of claim 13,wherein said distribution plugs are connected to said common power railvia respective input power isolation circuits.
 19. The powerdistribution system of claim 18, wherein said input power isolationcircuits further comprise respective diodes.